Provides researchers with an in-depth understanding of the challenges in verifying dynamically reconfigurable systems and the state-of-the-art methods used to overcome them

Guides engineers with systematic approaches and tools to achieve verification closure in their dynamically reconfigurable projects

Includes a comprehensive set of case studies, with an analysis of real bugs detected in the designs described

Uses tools and techniques compatible with mainstream products (e.g. Xilinx/Altera tools, Model Sim simulator, Verilog/VHDL design language, etc. …)

Details, step-by-step, how to design VLSI systems using Verilog

Provides hands-on experience on the popular industrial CAD tools

Shows the way to design systems that are device, vendor and technology independent

Offers thorough knowledge of cracking complex algorithms and mapping it on FPGA/ASIC

Prepares students to suit industries and research labs from day one