my_hw Project Status
Project File: wait2.xise Parser Errors: No Errors
Module Name: my_hw Implementation State: Synthesized
Target Device: xc6slx9-2tqg144
  • Errors:
No Errors
Product Version:ISE 14.2
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
 
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
  
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice Registers 4 11440 0%
Number of Slice LUTs 4 5720 0%
Number of fully used LUT-FF pairs 0 8 0%
Number of bonded IOBs 5 102 4%
Number of BUFG/BUFGCTRLs 1 16 6%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSun Jan 24 22:30:02 2016000
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 01/25/2016 - 15:23:45