my_hw Project Status
Project File: megawing.xise Parser Errors: No Errors
Module Name: my_hw Implementation State: Programming File Generated
Target Device: xc6slx9-2tqg144
  • Errors:
No Errors
Product Version:ISE 14.2
  • Warnings:
No Warnings
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers 37 11,440 1%  
    Number used as Flip Flops 37      
    Number used as Latches 0      
    Number used as Latch-thrus 0      
    Number used as AND/OR logics 0      
Number of Slice LUTs 106 5,720 1%  
    Number used as logic 104 5,720 1%  
        Number using O6 output only 33      
        Number using O5 output only 61      
        Number using O5 and O6 10      
        Number used as ROM 0      
    Number used as Memory 0 1,440 0%  
    Number used exclusively as route-thrus 2      
        Number with same-slice register load 0      
        Number with same-slice carry load 2      
        Number with other load 0      
Number of occupied Slices 29 1,430 2%  
Nummber of MUXCYs used 72 2,860 2%  
Number of LUT Flip Flop pairs used 109      
    Number with an unused Flip Flop 72 109 66%  
    Number with an unused LUT 3 109 2%  
    Number of fully used LUT-FF pairs 34 109 31%  
    Number of unique control sets 2      
    Number of slice register sites lost
        to control set restrictions
11 11,440 1%  
Number of bonded IOBs 29 102 28%  
    Number of LOCed IOBs 29 29 100%  
Number of RAMB16BWERs 0 32 0%  
Number of RAMB8BWERs 0 64 0%  
Number of BUFIO2/BUFIO2_2CLKs 0 32 0%  
Number of BUFIO2FB/BUFIO2FB_2CLKs 0 32 0%  
Number of BUFG/BUFGMUXs 1 16 6%  
    Number used as BUFGs 1      
    Number used as BUFGMUX 0      
Number of DCM/DCM_CLKGENs 0 4 0%  
Number of ILOGIC2/ISERDES2s 0 200 0%  
Number of IODELAY2/IODRP2/IODRP2_MCBs 0 200 0%  
Number of OLOGIC2/OSERDES2s 0 200 0%  
Number of BSCANs 0 4 0%  
Number of BUFHs 0 128 0%  
Number of BUFPLLs 0 8 0%  
Number of BUFPLL_MCBs 0 4 0%  
Number of DSP48A1s 0 16 0%  
Number of ICAPs 0 1 0%  
Number of MCBs 0 2 0%  
Number of PCILOGICSEs 0 2 0%  
Number of PLL_ADVs 0 2 0%  
Number of PMVs 0 1 0%  
Number of STARTUPs 0 1 0%  
Number of SUSPEND_SYNCs 0 1 0%  
Average Fanout of Non-Clock Nets 1.60      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentTue Jan 26 12:35:08 2016002 Infos (0 new)
Translation ReportCurrentTue Jan 26 12:35:15 2016000
Map ReportCurrentTue Jan 26 12:35:23 2016006 Infos (0 new)
Place and Route ReportCurrentTue Jan 26 12:35:31 2016003 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentTue Jan 26 12:35:36 2016004 Infos (0 new)
Bitgen ReportCurrentTue Jan 26 12:35:45 2016000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateTue Jan 26 12:35:45 2016
WebTalk Log FileOut of DateTue Jan 26 12:35:57 2016

Date Generated: 01/26/2016 - 15:05:08