example Project Status (01/26/2016 - 11:41:06) | |||
Project File: | example.xise | Parser Errors: | No Errors |
Module Name: | example | Implementation State: | Synthesized |
Target Device: | xc6slx9-2tqg144 |
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No Errors |
Product Version: | ISE 14.2 |
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No Warnings |
Design Goal: | Balanced |
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Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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Device Utilization Summary (estimated values) | [-] | |||
Logic Utilization | Used | Available | Utilization | |
Number of Slice LUTs | 7 | 5720 | 0% | |
Number of fully used LUT-FF pairs | 0 | 7 | 0% | |
Number of bonded IOBs | 12 | 102 | 11% |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Tue Jan 26 11:41:05 2016 | 0 | 0 | 0 | |
Translation Report | ||||||
Map Report | ||||||
Place and Route Report | ||||||
Power Report | ||||||
Post-PAR Static Timing Report | ||||||
Bitgen Report |
Secondary Reports | [-] | ||
Report Name | Status | Generated |